Messages in this thread | | | Date | Sat, 25 Jun 2022 08:32:53 +0300 | From | Nikita Shubin <> | Subject | Re: [PATCH v4 3/5] perf arch events: riscv arch std event files |
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Hello Atish!
On Fri, 24 Jun 2022 10:01:07 -0700 Atish Patra <atishp@atishpatra.org> wrote:
> On Fri, Jun 24, 2022 at 9:01 AM Nikita Shubin > <nikita.shubin@maquefel.me> wrote: > > > > From: Nikita Shubin <n.shubin@yadro.com> > > > > cycles, time and instret counters are defined by RISC-V privileged > > spec and they should be available on any RISC-V implementation, > > epose them to arch std event files, so they can be reused by > > particular PMU bindings. > > > > Derived-from-code-by: João Mário Domingos > > <joao.mario@tecnico.ulisboa.pt> Signed-off-by: Nikita Shubin > > <n.shubin@yadro.com> > > Why do we need this ? The PMU driver already parses the standard perf > events. So you can pass -e cycles -e instructions. > > Even though time is described as a counter and accessibility > controlled by mcounteren, you can not start/stop it (no bit in > mcountinhibit). > Thus, it can't be used from perf.
My first thought was that we can use cycle, time, instret on any RISC-V platform even without any bindings, but as you pointed out it's indeed useless.
I'll drop this one.
> > > --- > > .../pmu-events/arch/riscv/riscv-generic.json | 20 > > +++++++++++++++++++ 1 file changed, 20 insertions(+) > > create mode 100644 > > tools/perf/pmu-events/arch/riscv/riscv-generic.json > > > > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json > > b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode > > 100644 index 000000000000..a7ffbe87a0f7 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json > > @@ -0,0 +1,20 @@ > > +[ > > + { > > + "PublicDescription": "CPU Cycles", > > + "EventCode": "0x00", > > + "EventName": "riscv_cycles", > > + "BriefDescription": "CPU cycles RISC-V generic counter" > > + }, > > + { > > + "PublicDescription": "CPU Time", > > + "EventCode": "0x01", > > + "EventName": "riscv_time", > > + "BriefDescription": "CPU time RISC-V generic counter" > > + }, > > + { > > + "PublicDescription": "CPU Instructions", > > + "EventCode": "0x02", > > + "EventName": "riscv_instret", > > + "BriefDescription": "CPU retired instructions RISC-V generic > > counter" > > + } > > +] > > -- > > 2.35.1 > > > >
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