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SubjectRe: [PATCH] drm/bridge: add it6505 driver read config from dt property
Hi allen.

On Thu, Jun 23, 2022 at 05:31:54PM +0800, allen wrote:
> From: allen chen <allen.chen@ite.com.tw>
>
> add read max-lane and max-pixel-clock from dt property
>
> Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Can you fix so your s-o-b mail and author mail matches?
As it is now an error is flagged as they do not match.

Sam

> Signed-off-by: Pin-yen Lin <treapking@chromium.org>
> ---
> drivers/gpu/drm/bridge/ite-it6505.c | 35 ++++++++++++++++++++++++++---
> 1 file changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c
> index 4b673c4792d77..c9121d4635a52 100644
> --- a/drivers/gpu/drm/bridge/ite-it6505.c
> +++ b/drivers/gpu/drm/bridge/ite-it6505.c
> @@ -436,6 +436,8 @@ struct it6505 {
> bool powered;
> bool hpd_state;
> u32 afe_setting;
> + u32 max_dpi_pixel_clock;
> + u32 max_lane_count;
> enum hdcp_state hdcp_status;
> struct delayed_work hdcp_work;
> struct work_struct hdcp_wait_ksv_list;
> @@ -1466,7 +1468,8 @@ static void it6505_parse_link_capabilities(struct it6505 *it6505)
> it6505->lane_count = link->num_lanes;
> DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
> it6505->lane_count);
> - it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT);
> + it6505->lane_count = min_t(int, it6505->lane_count,
> + it6505->max_lane_count);
>
> it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
> DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
> @@ -2895,7 +2898,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge,
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> return MODE_NO_INTERLACE;
>
> - if (mode->clock > DPI_PIXEL_CLK_MAX)
> + if (mode->clock > it6505->max_dpi_pixel_clock)
> return MODE_CLOCK_HIGH;
>
> it6505->video_info.clock = mode->clock;
> @@ -3057,6 +3060,8 @@ static void it6505_parse_dt(struct it6505 *it6505)
> {
> struct device *dev = &it6505->client->dev;
> u32 *afe_setting = &it6505->afe_setting;
> + u32 *max_lane_count = &it6505->max_lane_count;
> + u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
>
> it6505->lane_swap_disabled =
> device_property_read_bool(dev, "no-laneswap");
> @@ -3072,7 +3077,31 @@ static void it6505_parse_dt(struct it6505 *it6505)
> } else {
> *afe_setting = 0;
> }
> - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting);
> +
> + if (device_property_read_u32(dev, "max-lane-count",
> + max_lane_count) == 0) {
> + if (*max_lane_count > 4 || *max_lane_count == 3) {
> + dev_err(dev, "max lane count error, use default");
> + *max_lane_count = MAX_LANE_COUNT;
> + }
> + } else {
> + *max_lane_count = MAX_LANE_COUNT;
> + }
> +
> + if (device_property_read_u32(dev, "max-dpi-pixel-clock",
> + max_dpi_pixel_clock) == 0) {
> + if (*max_dpi_pixel_clock > 297000) {
> + dev_err(dev, "max pixel clock error, use default");
> + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
> + }
> + } else {
> + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
> + }
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
> + it6505->afe_setting, it6505->max_lane_count);
> + DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
> + it6505->max_dpi_pixel_clock);
> }
>
> static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
> --
> 2.25.1

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