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Subject[PATCH 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC
Date
Document Renesas RZ/Five (R9A07G043) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
RFC->v1:
* Fixed Review comments pointed by Geert and Rob
---
.../sifive,plic-1.0.0.yaml | 40 +++++++++++++++++--
1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 27092c6a86c4..5eebe0b01b4d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -28,7 +28,10 @@ description:

While the PLIC supports both edge-triggered and level-triggered interrupts,
interrupt handlers are oblivious to this distinction and therefore it is not
- specified in the PLIC device-tree binding.
+ specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
+ but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
+ to specify the interrupt type as the flow for EDGE interrupts is different
+ compared to LEVEL interrupts.

While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -57,6 +60,7 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
+ - const: renesas,r9a07g043-plic

reg:
maxItems: 1
@@ -64,8 +68,7 @@ properties:
'#address-cells':
const: 0

- '#interrupt-cells':
- const: 1
+ '#interrupt-cells': true

interrupt-controller: true

@@ -91,7 +94,36 @@ required:
- interrupts-extended
- riscv,ndev

-additionalProperties: false
+if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g043-plic
+then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 2
+
+ required:
+ - clocks
+ - resets
+ - power-domains
+
+else:
+ properties:
+ '#interrupt-cells':
+ const: 1
+
+unevaluatedProperties: false

examples:
- |
--
2.25.1
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