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SubjectRe: [PING^2][PATCH] RISC-V: PCI: Avoid handing out address 0 to devices
On Wed, 22 Jun 2022, Palmer Dabbelt wrote:

> > > Therefore avoid handing out address 0, by bumping the lowest address
> > > available to PCI via PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM up by 4 and 16
> > > respectively, which is the minimum allocation size for I/O and memory
> > > BARs.
> >
> > Ping for:
> > <https://lore.kernel.org/lkml/alpine.DEB.2.21.2204271207590.9383@angie.orcam.me.uk/>
>
> Sorry, I got this mixed up with the non-RISC-V patch.

If you mean this:

<https://lore.kernel.org/lkml/alpine.DEB.2.21.2202260044180.25061@angie.orcam.me.uk/>

then we just don't have consensus to move forward. If we ever do for a
generic change, then we can revert the RISC-V platform solution, as it's
merely an internal implementation detail and not a part of the ABI or
something.

> David poked me about
> it, this is on for-next. It's passing my tests, but they're just QEMU so
> probably not all that exciting here.

Thanks! I don't know offhand what QEMU supports as far as the RISC-V
architecture is concerned; I guess you can't just enable a PCI port-I/O
serial port in the simulator and see if it works with Linux or not.

Anyway it's just number shuffling, so the change should be reasonably
safe.

Maciej

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