Messages in this thread | | | Date | Fri, 24 Jun 2022 12:40:26 -0400 | From | Brian Masney <> | Subject | Re: [PATCH] clk: qcom: sc8280xp: add parent to gcc_ufs_phy_axi_clk for sa8540p |
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On Thu, Jun 23, 2022 at 05:20:53PM -0700, Stephen Boyd wrote: > Quoting Brian Masney (2022-06-23 07:28:37) > > diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c > > index 4b894442fdf5..4639b50da418 100644 > > --- a/drivers/clk/qcom/gcc-sc8280xp.c > > +++ b/drivers/clk/qcom/gcc-sc8280xp.c > > @@ -5696,6 +5709,7 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { > > .hw.init = &(const struct clk_init_data) { > > .name = "gcc_ufs_phy_axi_clk", > > .parent_hws = (const struct clk_hw*[]){ > > + &gcc_ufs_ref_clkref_clk.clkr.hw, > > &gcc_ufs_phy_axi_clk_src.clkr.hw, > > }, > > .num_parents = 1, > > num_parents needs an update.
Oops!
> But this is a branch, not a mux, so it can't have more than one > parent.
Would a mux be represented with 'struct clk_rcg2'?
Brian
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