Messages in this thread | | | Date | Fri, 24 Jun 2022 09:59:42 +0200 | Subject | Re: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents | From | Krzysztof Kozlowski <> |
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On 26/05/2022 09:21, Krzysztof Kozlowski wrote: > On 26/05/2022 07:58, David Virag wrote: >> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by >> 2 to achieve a by 4 division, thus their parents are the respective >> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents. >> This leads to the kernel thinking "div4"s and everything under them run >> at 2x the clock speed. Fix this. >> >> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver") >> Signed-off-by: David Virag <virag.david003@gmail.com> >> --- >> drivers/clk/samsung/clk-exynos7885.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-)
Sylwester,
This goes to v5.20?
Best regards, Krzysztof
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