Messages in this thread | | | From | Doug Anderson <> | Date | Thu, 23 Jun 2022 16:11:48 -0700 | Subject | Re: [PATCH] tty: serial: qcom-geni-serial: minor fixes to get_clk_div_rate() |
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Hi,
On Tue, Jun 21, 2022 at 10:58 AM Vijaya Krishna Nivarthi (Temp) <vnivarth@qti.qualcomm.com> wrote: > > Hi, > > For desired_clk = 100 and clock rates like 1st from below, DIV_ROUND_UP seems to cause missing candidate solutions. > > static unsigned long clk_round_rate_test(struct clk *clk, unsigned long in_freq) > { > //unsigned long root_freq[] = {301, 702, 1004}; > //unsigned long root_freq[] = {301, 702, 1004, 2000, 3000}; > //unsigned long root_freq[] = {50, 97, 99}; > //unsigned long root_freq[] = {50, 97, 99, 200}; > //unsigned long root_freq[] = {92, 110, 193, 230}; > //unsigned long root_freq[] = {92, 110, 193, 230, 300, 401}; > //unsigned long root_freq[] = {92, 110, 193, 230, 295, 296, 297, 401}; > //unsigned long root_freq[] = {92, 110, 193, 230, 295, 296, 297, 300, 401}; > //unsigned long root_freq[] = {197, 198, 199}; > unsigned long root_freq[] = {197, 198, 199, 200}; > int i; > size_t n = sizeof root_freq / sizeof *root_freq; > > for (i = 0; i < n; i++) { > if (root_freq[i] >= in_freq) > return root_freq[i]; > } > return root_freq[n-1]; > } > > I modified to handle such cases, optimised little and uploaded a patch. > It seems to work for all the cases like above.
I think it would have been simpler to just change this little section:
/* Save the first (lowest freq) within 2% */ actual_mult = DIV_ROUND_CLOSEST(freq, desired_clk) * desired_clk; if (!ser_clk && freq <= actual_mult + two_percent) { ser_clk = freq; *clk_div = div; }
That was the only bug, right? Then you could keep the DIV_ROUND_UP() solution?
-Doug
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