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    Subject[PATCH 07/14] arm64: dts: imx8mp-evk: correct I2C5 pad settings
    Date
    From: Peng Fan <peng.fan@nxp.com>

    According to RM bit layout, BIT3 and BIT0 are reserved.
    8 7 6 5 4 3 2 1 0
    PE HYS PUE ODE FSEL X DSE X

    Although function is not broken, we should not set reserved bit.

    Fixes: 8134822db08d ("arm64: dts: imx8mp-evk: add support for I2C5")
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    ---
    arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
    index ce4556dab385..defba22da183 100644
    --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
    +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
    @@ -497,8 +497,8 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3

    pinctrl_i2c5: i2c5grp {
    fsl,pins = <
    - MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
    - MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
    + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
    + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
    >;
    };

    --
    2.25.1
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