Messages in this thread Patch in this message | | | From | Amit Kumar Mahapatra <> | Subject | [PATCH v2 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR | Date | Tue, 21 Jun 2022 14:25:00 +0530 |
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From: Olga Kitaina <okitain@gmail.com>
According to the Arasan NAND controller spec, the flash clock rate for SDR must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the CLK line for the mode. The driver previously always set 100 MHz for NV-DDR, which would result in incorrect behavior for NV-DDR modes 0-4.
The appropriate clock rate can be calculated from the NV-DDR timing parameters as 1/tCK, or for rates measured in picoseconds, 10^12 / nand_nvddr_timings->tCK_min.
Signed-off-by: Olga Kitaina <okitain@gmail.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> --- drivers/mtd/nand/raw/arasan-nand-controller.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index 4f6da82dd2b1..0eff069d7f80 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -1044,10 +1044,20 @@ static int anfc_setup_interface(struct nand_chip *chip, int target, DQS_BUFF_SEL_OUT(dqs_mode); } - ret = clk_set_rate(nfc->bus_clk, ANFC_XLNX_SDR_DFLT_CORE_CLK); - if (ret) { - dev_err(nfc->dev, "Failed to change bus clock rate\n"); - return ret; + if (nand_interface_is_sdr(conf)) { + ret = clk_set_rate(nfc->bus_clk, ANFC_XLNX_SDR_DFLT_CORE_CLK); + if (ret) { + dev_err(nfc->dev, "Failed to change bus clock rate\n"); + return ret; + } + } else { + /* ONFI timings are defined in picoseconds */ + ret = clk_set_rate(nfc->bus_clk, div_u64((u64)NSEC_PER_SEC * 1000, + conf->timings.nvddr.tCK_min)); + if (ret) { + dev_err(nfc->dev, "Failed to change bus clock rate\n"); + return ret; + } } /* -- 2.17.1
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