Messages in this thread | | | Date | Mon, 20 Jun 2022 18:02:32 +0800 | Subject | Re: [External] [PATCH v9 9/9] KVM: VMX: enable IPI virtualization | From | Shenming Lu <> |
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On 19/04/2022 23:45, Zeng Guang wrote: > From: Chao Gao <chao.gao@intel.com> > > With IPI virtualization enabled, the processor emulates writes to > APIC registers that would send IPIs. The processor sets the bit > corresponding to the vector in target vCPU's PIR and may send a > notification (IPI) specified by NDST and NV fields in target vCPU's > Posted-Interrupt Descriptor (PID). It is similar to what IOMMU > engine does when dealing with posted interrupt from devices. >
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> @@ -3872,6 +3875,8 @@ static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu) > vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW); > vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); > vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); > + if (enable_ipiv) > + vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW); > } > } > > @@ -4195,14 +4200,19 @@ static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) > > pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); > > - if (kvm_vcpu_apicv_active(vcpu)) > + if (kvm_vcpu_apicv_active(vcpu)) { > secondary_exec_controls_setbit(vmx, > SECONDARY_EXEC_APIC_REGISTER_VIRT | > SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); > - else > + if (enable_ipiv) > + tertiary_exec_controls_setbit(vmx, TERTIARY_EXEC_IPI_VIRT); > + } else { > secondary_exec_controls_clearbit(vmx, > SECONDARY_EXEC_APIC_REGISTER_VIRT | > SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); > + if (enable_ipiv) > + tertiary_exec_controls_clearbit(vmx, TERTIARY_EXEC_IPI_VIRT); > + } > > vmx_update_msr_bitmap_x2apic(vcpu); > }
Hi, just a small question here:
It seems that we clear the TERTIARY_EXEC_IPI_VIRT bit before enabling interception for APIC_ICR when deactivating APICv on some reason. Is there any problem with this sequence?
Thanks, shenming
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