Messages in this thread | | | From | Christoph Müllner <> | Date | Thu, 2 Jun 2022 18:32:06 +0200 | Subject | Re: [RFC PATCH] riscv: Add Zawrs support for spinlocks |
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On Thu, Jun 2, 2022 at 6:24 PM Randy Dunlap <rdunlap@infradead.org> wrote: > > Hi-- > > On 6/2/22 07:10, Christoph Muellner wrote: > > The current RISC-V code uses the generic ticket lock implementation, > > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). > > Currently, RISC-V uses the generic implementation of these macros. > > This patch introduces a RISC-V specific implementation, of these > > macros, that peels off the first loop iteration and modifies the waiting > > loop such, that it is possible to use the WRS instruction of the Zawrs > > ISA extension to stall the CPU. > > > > The resulting implementation of smp_cond_load_*() will only work for > > 32-bit or 64-bit types for RV64 and 32-bit types for RV32. > > This is caused by the restrictions of the LR instruction (RISC-V only > > has LR.W and LR.D). Compiler assertions guard this new restriction. > > > > This patch uses the existing RISC-V ISA extension framework > > to detect the presents of Zawrs at run-time. > > If available a NOP instruction will be replaced by WRS. > > A similar patch could add support for the PAUSE instruction of > > the Zihintpause ISA extension. > > > > The whole mechanism is gated by Kconfig setting, which defaults to Y. > > > > The Zawrs specification can be found here: > > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > > > Note, that the Zawrs extension is not frozen or ratified yet. > > Therefore this patch is an RFC and not intended to get merged. > > > > Signed-off-by: Christoph Muellner <christoph.muellner@vrull.io> > > --- > > arch/riscv/Kconfig | 10 +++ > > arch/riscv/include/asm/barrier.h | 97 ++++++++++++++++++++++++++++ > > arch/riscv/include/asm/errata_list.h | 12 +++- > > arch/riscv/include/asm/hwcap.h | 3 +- > > arch/riscv/kernel/cpu.c | 1 + > > arch/riscv/kernel/cpufeature.c | 13 ++++ > > 6 files changed, 133 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 905e550e0fd3..054872317d4a 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -358,6 +358,16 @@ config RISCV_ISA_C > > > > If you don't know what to do here, say Y. > > > > +config RISCV_ISA_ZAWRS > > + bool "Zawrs extension support" > > + select RISCV_ALTERNATIVE > > + default y > > + help > > + Adds support to dynamically detect the presence of the Zawrs extension > > + (wait for reservation set) and enable its usage. > > + > > + If you don't know what to do here, say Y. > > + > > With this patch, it is possible to enable XIP_KERNEL and > RISCV_ISA_ZAWRS at the same time. That causes a kconfig warning: > > WARNING: unmet direct dependencies detected for RISCV_ALTERNATIVE > Depends on [n]: !XIP_KERNEL [=y] > Selected by [y]: > - RISCV_ISA_ZAWRS [=y] > - RISCV_ISA_SVPBMT [=y] && 64BIT [=y] && MMU [=y] > > because RISCV_ALTERNATIVE depends on !XIP_KERNEL: > > config RISCV_ALTERNATIVE > bool > depends on !XIP_KERNEL
I will add a "depends on !XIP_KERNEL" to RISCV_ISA_ZAWRS.
Thanks!
> > > > config RISCV_ISA_SVPBMT > > bool "SVPBMT extension support" > > depends on 64BIT && MMU > > > -- > ~Randy
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