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    Subject[RFC 0/6] PolarFire SoC Reset controller
    Date
    From: Conor Dooley <conor.dooley@microchip.com>

    Hi Stephen (& Philipp),

    I gave the aux bus approach to the clock->reset driver combo a go.
    Could you take a quick look and lmk if it meets your expectations
    for that approach? There weren't too many aux bus drivers to "take
    inspiration from" so I implemented this based on drivers/peci/cpu.c
    If it all looks sane at first glance, I'll tidy things up a little
    and submit.

    @Geert the prior "RFC" you said you saw issues with the ethernet?
    I implemented the reset stuff for the macs and it looks to be to
    be working fine - but I did not do any meaninful testing with
    CONFIG_PM=y.

    Thanks,
    Conor.

    (Since it's just the clk -> reset aux bus interface I care about
    here, I left the net/dt maintainers off the CC.)*

    Conor Dooley (6):
    dt-bindings: clk: microchip: mpfs: add reset controller support
    dt-bindings: net: cdns,macb: document polarfire soc's macb
    clk: microchip: mpfs: add reset controller
    reset: add polarfire soc reset support
    net: macb: add polarfire soc reset support
    riscv: dts: microchip: add mpfs specific macb reset support

    .../bindings/clock/microchip,mpfs.yaml | 17 +-
    .../devicetree/bindings/net/cdns,macb.yaml | 1 +
    arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +-
    drivers/clk/microchip/Kconfig | 1 +
    drivers/clk/microchip/clk-mpfs.c | 118 +++++++++++--
    drivers/net/ethernet/cadence/macb_main.c | 25 ++-
    drivers/reset/Kconfig | 9 +
    drivers/reset/Makefile | 2 +-
    drivers/reset/reset-mpfs.c | 155 ++++++++++++++++++
    include/soc/microchip/mpfs.h | 8 +
    10 files changed, 320 insertions(+), 23 deletions(-)
    create mode 100644 drivers/reset/reset-mpfs.c


    base-commit: b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3
    --
    2.36.1

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