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SubjectRe: [PATCH 1/2] dt-bindings: phy: Add Freescale i.MX8qm Mixel LVDS PHY binding
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On 18/06/2022 11:22, Liu Ying wrote:
> This patch adds bindings for Mixel LVDS PHY found on
> Freescale i.MX8qm SoC.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> .../bindings/phy/mixel,lvds-phy.yaml | 64 +++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> new file mode 100644
> index 000000000000..de964ffb9356
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mixel,lvds-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mixel LVDS PHY for Freescale i.MX8qm SoC

If Mixel is a vendor, it needs it's vendor prefix documented and used in
compatible. Filename should match compatible. If it is not a vendor,
then filename should be "fsl,imx8qm-lvds-phy.yaml"

> +
> +maintainers:
> + - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> + The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
> + It converts two groups of four 7/10 bits of CMOS data into two
> + groups of four data lanes of LVDS data streams. A phase-locked
> + transmit clock is transmitted in parallel with each group of
> + data streams over a fifth LVDS link. Every cycle of the transmit
> + clock, 56/80 bits of input data are sampled and transmitted
> + through the two groups of LVDS data streams. Together with the
> + transmit clocks, the two groups of LVDS data streams form two
> + LVDS channels.
> +
> + The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
> + by Control and Status Registers(CSR) module in the SoC. The CSR
> + module, as a system controller, contains the PHY's registers.
> +
> +properties:
> + compatible:
> + const: fsl,imx8qm-lvds-phy
> +
> + "#phy-cells":
> + const: 1
> + description: |
> + Cell allows setting the LVDS channel index of the PHY.
> + Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: phy_ref

Maybe just skip the clock-names, it's not bringing anything useful,
unless you expect some more clocks to be documented later? (but in such
case question would be why they are not documented now)

> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - "#phy-cells"
> + - clocks
> + - clock-names
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + phy {
> + compatible = "fsl,imx8qm-lvds-phy";
> + #phy-cells = <1>;
> + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
> + clock-names = "phy_ref";
> + power-domains = <&pd IMX_SC_R_LVDS_0>;
> + };


Best regards,
Krzysztof

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