Messages in this thread | | | Subject | Re: [PATCH v2 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent | From | Rex-BC Chen <> | Date | Fri, 17 Jun 2022 18:10:42 +0800 |
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On Fri, 2022-06-17 at 17:34 +0800, AngeloGioacchino Del Regno wrote: > Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), > add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) > and also fix its parent clock name as it has to be "top_dp" for two > reasons: > - This is its real parent! > - Likewise to eDP/VDO0 counterpart, we need clock source > selection on CLK_TOP_DP. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock > support") > Hello Angelo,
Thanks for this series. I can use this series to do modetest using MT8195 Tomato Chromebook for both dp and edp in kernel v5.19-rc1.
Therefore, Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> and, Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
BRs, Bo-Chen
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