Messages in this thread | | | Subject | Re: [PATCH v2 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent | From | Rex-BC Chen <> | Date | Fri, 17 Jun 2022 18:10:03 +0800 |
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On Fri, 2022-06-17 at 17:34 +0800, AngeloGioacchino Del Regno wrote: > Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF > clock: this is required to trigger clock source selection on > CLK_TOP_EDP, while avoiding to manage the enablement of the former > separately from the latter in the displayport driver. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock > support") > ---
Hello Angelo,
Thanks for this series. I can use this series to do modetest using MT8195 Tomato Chromebook for both dp and edp in kernel v5.19-rc1.
Therefore, Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> and, Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
BRs, Bo-Chen
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