Messages in this thread Patch in this message | | | Date | Thu, 16 Jun 2022 15:58:37 -0700 | Subject | Re: [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy | From | Krzysztof Kozlowski <> |
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On 13/06/2022 18:29, Wangseok Lee wrote: > Add description to support Axis, ARTPEC-8 SoC. > ARTPEC-8 is the SoC platform of Axis Communications > and PCIe phy is designed based on SAMSUNG PHY.
No improvements here. On v2 I gave you link pointing to specific paragraph of our documentation which you need to apply - wrong wrapping. Is there something unclear here?
Please do not wrap in different style.
> > Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> > --- > v2->v3 : > -modify version history to fit the linux commit rule > -remove 'Device Tree Bindings' on title > -remove clock-names entries > -change node name to soc from artpec8 on excamples > > v1->v2 : > -'make dt_binding_check' result improvement > -Add the missing property list > -Align the indentation of continued lines/entries > --- > .../bindings/phy/axis,artpec8-pcie-phy.yaml | 73 ++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > new file mode 100644 > index 0000000..316b774 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARTPEC-8 SoC PCIe PHY > + > +maintainers: > + - Jesper Nilsson <jesper.nilsson@axis.com> > + > +properties: > + compatible: > + const: axis,artpec8-pcie-phy > + > + reg: > + items: > + - description: PHY registers. > + - description: PHY coding sublayer registers. > + > + reg-names: > + items: > + - const: phy > + - const: pcs > + > + "#phy-cells": > + const: 0 > + > + clocks: > + items: > + - description: PCIe PHY reference clock > + > + num-lanes: > + const: 2 > + > + lcpll-ref-clk: > + const: 1 Unknown field... custom properties need vendor (axis,), type (boolean) and description.
> + > +required: > + - compatible > + - reg > + - reg-names > + - "#phy-cells" > + - clocks > + - clock-names > + - samsung,fsys-sysreg
Same problem as in patch #1.
> + - num-lanes > + - lcpll-ref-clk > + > +additionalProperties: true
No, this must be false.
Best regards, Krzysztof
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