Messages in this thread | | | From | Linus Walleij <> | Date | Wed, 15 Jun 2022 15:23:57 +0200 | Subject | Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes |
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On Mon, May 30, 2022 at 2:35 PM Fabien Parent <fparent@baylibre.com> wrote:
> On MT8365, the SET/CLR of the mode is broken and some pin modes won't > be set correctly. Add a quirk for such SoCs, so that instead of using > the SET/CLR register use the main R/W register > to read/update/write the modes. > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
What is the state of this patch set? I see changes are requested by Angelo, are they being addressed?
Yours, Linus Walleij
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