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SubjectRe: [PATCH v1] PCI: qcom: Allow L1 and its sub states on qcom dwc wrapper
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On 6/9/2022 4:56 PM, Manivannan Sadhasivam wrote:
> On Fri, Jun 03, 2022 at 12:48:50PM +0530, Krishna chaitanya chundru wrote:
>> Allow L1 and its sub-states in the qcom dwc pcie wrapper.
> s/wrapper/driver
>
> Also there is no need to use "qcom dwc" in subject. Prefix makes it explicit.
Sure will update in the next patch.
>> By default its disabled. So enable it explicitly.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 6ab9089..f60645c 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -41,6 +41,9 @@
>> #define L23_CLK_RMV_DIS BIT(2)
>> #define L1_CLK_RMV_DIS BIT(1)
>>
>> +#define PCIE20_PARF_PM_CTRL 0x20
>> +#define REQ_NOT_ENTR_L1 BIT(5)
>> +
>> #define PCIE20_PARF_PHY_CTRL 0x40
>> #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
>> #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
>> @@ -1267,6 +1270,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>> val |= BIT(4);
>> writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>>
>> + /* Clear PARF PM REQ_NOT_ENTR_L1 bit to allow L1 states */
> Mentioning the field in comment is redundant. Just say "Enable L1 and L1ss"
sure will update in the next patch.
> Thanks,
> Mani
>
>> + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL);
>> + val &= ~REQ_NOT_ENTR_L1;
>> + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);
>> +
>> if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
>> val |= BIT(31);
>> --
>> 2.7.4
>>

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