Messages in this thread Patch in this message | | | From | Wolfram Sang <> | Subject | [PATCH v2] arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector | Date | Tue, 14 Jun 2022 21:30:05 +0200 |
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The schematics label it as SCIF0 debug port.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> ---
Change since v1: added alias
.../arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider.dts | 1 + 2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 3208d2148768..7a62afb64204 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -68,6 +68,11 @@ i2c4_pins: i2c4 { function = "i2c4"; }; + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; @@ -79,6 +84,14 @@ &rwdt { status = "okay"; }; +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &scif_clk { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index 954ba227bfa7..2c1fe4330c2b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -15,6 +15,7 @@ / { aliases { serial0 = &hscif0; + serial1 = &scif0; }; chosen { -- 2.35.1
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