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SubjectRe: [PATCH v11 01/12] dt-bindings: mediatek,dpi: Add DP_INTF compatible
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Hi, Bo-Chen:

On Mon, 2022-06-13 at 14:48 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann <msp@baylibre.com>
>
> DP_INTF is similar to DPI but does not have the exact same feature
> set
> or register layouts.
>
> DP_INTF is the sink of the display pipeline that is connected to the
> DisplayPort controller and encoder unit. It takes the same clocks as
> DPI.
>
> In this patch, we also do these string replacement:
> - s/mediatek/MediaTek/ in title.
> - s/Mediatek/MediaTek/ in description.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
> .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++---
> --
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam
> l
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam
> l
> index 77ee1b923991..ca1b48e78581 100644
> ---
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam
> l
> +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam
> l
> @@ -4,16 +4,16 @@
> $id:
> http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: mediatek DPI Controller Device Tree Bindings
> +title: MediaTek DPI and DP_INTF Controller
>
> maintainers:
> - CK Hu <ck.hu@mediatek.com>
> - Jitao shi <jitao.shi@mediatek.com>
>
> description: |
> - The Mediatek DPI function block is a sink of the display subsystem
> and
> - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
> parallel
> - output bus.
> + The MediaTek DPI and DP_INTF function blocks are a sink of the
> display
> + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422
> pixel data on a
> + parallel output bus.
>
> properties:
> compatible:
> @@ -24,6 +24,7 @@ properties:
> - mediatek,mt8183-dpi
> - mediatek,mt8186-dpi
> - mediatek,mt8192-dpi
> + - mediatek,mt8195-dp_intf
>
> reg:
> maxItems: 1
> @@ -36,12 +37,14 @@ properties:
> - description: Pixel Clock
> - description: Engine Clock
> - description: DPI PLL
> + - description: Clock gate for PLL

Why DP_INTF has this additional clock? What is the new hardware block
(compared with DPI) need this clock? Why this is different than DPI?

Regards,
CK

>
> clock-names:
> items:
> - const: pixel
> - const: engine
> - const: pll
> + - const: pll_gate
>
> pinctrl-0: true
> pinctrl-1: true
> @@ -55,7 +58,7 @@ properties:
> $ref: /schemas/graph.yaml#/properties/port
> description:
> Output port node. This port should be connected to the input
> port of an
> - attached HDMI or LVDS encoder chip.
> + attached HDMI, LVDS or DisplayPort encoder chip.
>
> required:
> - compatible

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