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    Subject[PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
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    Add description to support Axis, ARTPEC-8 SoC.
    ARTPEC-8 is the SoC platform of Axis Communications
    and PCIe phy is designed based on SAMSUNG PHY.

    Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>
    ---
    v2->v3 :
    -modify version history to fit the linux commit rule
    -remove 'Device Tree Bindings' on title
    -remove clock-names entries
    -change node name to soc from artpec8 on excamples

    v1->v2 :
    -'make dt_binding_check' result improvement
    -Add the missing property list
    -Align the indentation of continued lines/entries
    ---
    .../bindings/phy/axis,artpec8-pcie-phy.yaml | 73 ++++++++++++++++++++++
    1 file changed, 73 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml

    diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
    new file mode 100644
    index 0000000..316b774
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
    @@ -0,0 +1,73 @@
    +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: ARTPEC-8 SoC PCIe PHY
    +
    +maintainers:
    + - Jesper Nilsson <jesper.nilsson@axis.com>
    +
    +properties:
    + compatible:
    + const: axis,artpec8-pcie-phy
    +
    + reg:
    + items:
    + - description: PHY registers.
    + - description: PHY coding sublayer registers.
    +
    + reg-names:
    + items:
    + - const: phy
    + - const: pcs
    +
    + "#phy-cells":
    + const: 0
    +
    + clocks:
    + items:
    + - description: PCIe PHY reference clock
    +
    + num-lanes:
    + const: 2
    +
    + lcpll-ref-clk:
    + const: 1
    +
    +required:
    + - compatible
    + - reg
    + - reg-names
    + - "#phy-cells"
    + - clocks
    + - clock-names
    + - samsung,fsys-sysreg
    + - num-lanes
    + - lcpll-ref-clk
    +
    +additionalProperties: true
    +
    +examples:
    + - |
    + #include <dt-bindings/interrupt-controller/irq.h>
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    +
    + soc {
    + #address-cells = <2>;
    + #size-cells = <2>;
    + pcie_phy: pcie-phy@16c80000 {
    + compatible = "axis,artpec8-pcie-phy";
    + reg = <0x0 0x16c80000 0x0 0x2000>,
    + <0x0 0x16c90000 0x0 0x1000>;
    + reg-names = "phy", "pcs";
    + #phy-cells = <0>;
    + clocks = <&clock_cmu_fsys 53>;
    + clock-names = "ref";
    + samsung,fsys-sysreg = <&syscon_fsys>;
    + num-lanes = <2>;
    + lcpll-ref-clk = <1>;
    + };
    + };
    +...
    --
    2.9.5
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