Messages in this thread | | | Date | Wed, 1 Jun 2022 09:06:40 -0700 | From | <> | Subject | Re: [PATCH v6 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings |
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On 6/1/22 5:22 AM, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 01/06/2022 01:43, Tanmay Shah wrote: > > Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing > > Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem > > (cluster). > > > > Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com> > > --- > > > > Changes in v6: > > - Add maxItems to sram and memory-region property > > > > Changes in v5: > > - Add constraints of the possible values of xlnx,cluster-mode property > > - fix description of power-domains property for r5 core > > - Remove reg, address-cells and size-cells properties as it is not required > > - Fix description of mboxes property > > - Add description of each memory-region and remove old .txt binding link > > reference in the description > > > > Changes in v4: > > - Add memory-region, mboxes and mbox-names properties in example > > > > Changes in v3: > > - None > > > > > > .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ > > include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + > > 2 files changed, 135 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > new file mode 100644 > > index 000000000000..cbff1c201a89 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > @@ -0,0 +1,129 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Xilinx R5F processor subsystem > > + > > +maintainers: > > + - Ben Levinsky <ben.levinsky@xilinx.com> > > + - Tanmay Shah <tanmay.shah@xilinx.com> > > + > > +description: | > > + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for > > + real-time processing based on the Cortex-R5F processor core from ARM. > > + The Cortex-R5F processor implements the Arm v7-R architecture and includes a > > + floating-point unit that implements the Arm VFPv3 instruction set. > > + > > +properties: > > + compatible: > > + const: xlnx,zynqmp-r5fss > > + > > + xlnx,cluster-mode: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [0, 1, 2] > > + description: | > > + The RPU MPCore can operate in split mode(Dual-processor performance), Safety > > + lock-step mode(Both RPU cores execute the same code in lock-step, > > + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while > > + core 1 runs normally). The processor does not support dynamic configuration. > > + Switching between modes is only permitted immediately after a processor reset. > > + If set to 1 then lockstep mode and if 0 then split mode. > > + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. > > + > > +patternProperties: > > + "^r5f-[a-f0-9]+$": > > + type: object > > + description: | > > + The RPU is located in the Low Power Domain of the Processor Subsystem. > > + Each processor includes separate L1 instruction and data caches and > > + tightly coupled memories (TCM). System memory is cacheable, but the TCM > > + memory space is non-cacheable. > > + > > + Each RPU contains one 64KB memory and two 32KB memories that > > + are accessed via the TCM A and B port interfaces, for a total of 128KB > > + per processor. In lock-step mode, the processor has access to 256KB of > > + TCM memory. > > + > > + properties: > > + compatible: > > + const: xlnx,zynqmp-r5f > > + > > + power-domains: > > + description: RPU core PM domain specifier > > + maxItems: 1 > > + > > + mboxes: > > + minItems: 1 > > + items: > > + - description: mailbox channel to send data to RPU > > + - description: mailbox channel to receive data from RPU > > + > > + mbox-names: > > + minItems: 1 > > + items: > > + - const: tx > > + - const: rx > > + > > + sram: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + maxItems: 8 > > Without minItems, this means maxItems=minItems and previously you had > here "minItems:1", so is it really what you want? >
Ok. I misunderstood previous comment here in that case. I thought minIterms will be 1 by default. But, it is not that way. I will fix this in next revision.
Thanks.
> Anyway rest looks good to me. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Best regards, > Krzysztof >
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