Messages in this thread Patch in this message | | | From | Sibi Sankar <> | Subject | [PATCH 1/3] dt-bindings: interconnect: Update email address | Date | Thu, 2 Jun 2022 06:18:41 +0530 |
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Update email address to the quicinc.com domain.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 116e434d0daa..bf538c0c5a81 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider maintainers: - - Sibi Sankar <sibis@codeaurora.org> + - Sibi Sankar <quic_sibis@quicinc.com> description: L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. -- 2.7.4
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