Messages in this thread Patch in this message | | | From | Fabien Parent <> | Subject | [PATCH 2/2] pinctrl: mediatek: mt8365: use MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk | Date | Mon, 30 May 2022 14:34:25 +0200 |
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On MT8365, the GPIO64 modes cannot be set using the SET/CLR register. Use the MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk to workaround it.
Signed-off-by: Fabien Parent <fparent@baylibre.com> --- drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 57f37a294063..a49fa685f5f5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -454,6 +454,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .ap_num = 160, .db_cnt = 160, }, + .quirks = MTK_PINCTRL_MODE_SET_CLR_BROKEN, }; static const struct of_device_id mt8365_pctrl_match[] = { -- 2.36.1
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