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    SubjectRe: [PATCH v2 6/8] clk: qcom: add support for SM8350 DISPCC
    On Tue 03 May 08:04 CDT 2022, Robert Foss wrote:

    > From: Jonathan Marek <jonathan@marek.ca>
    >
    > Add support to the SM8350 display clock controller by extending the SM8250
    > display clock controller, which is almost identical but has some minor
    > differences.
    >
    > Signed-off-by: Jonathan Marek <jonathan@marek.ca>
    > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

    You handled this patch, as such your S-o-b should be here as well.

    The rest looks good to me.

    Regards,
    Bjorn

    > ---
    >
    > Changes since v1
    > - Remove comment - Dmitry
    >
    >
    > drivers/clk/qcom/Kconfig | 4 +--
    > drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++-
    > 2 files changed, 61 insertions(+), 3 deletions(-)
    >
    > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
    > index 9b1f54e634b9..1752ca0ee405 100644
    > --- a/drivers/clk/qcom/Kconfig
    > +++ b/drivers/clk/qcom/Kconfig
    > @@ -609,11 +609,11 @@ config SM_DISPCC_6125
    > splash screen
    >
    > config SM_DISPCC_8250
    > - tristate "SM8150 and SM8250 Display Clock Controller"
    > + tristate "SM8150/SM8250/SM8350 Display Clock Controller"
    > depends on SM_GCC_8150 || SM_GCC_8250
    > help
    > Support for the display clock controller on Qualcomm Technologies, Inc
    > - SM8150 and SM8250 devices.
    > + SM8150/SM8250/SM8350 devices.
    > Say Y if you want to support display devices and functionality such as
    > splash screen.
    >
    > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
    > index 22d9cbabecab..daa3714cfc7d 100644
    > --- a/drivers/clk/qcom/dispcc-sm8250.c
    > +++ b/drivers/clk/qcom/dispcc-sm8250.c
    > @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = {
    > { 249600000, 2000000000, 0 },
    > };
    >
    > +static struct pll_vco lucid_5lpe_vco[] = {
    > + { 249600000, 1750000000, 0 },
    > +};
    > +
    > static struct alpha_pll_config disp_cc_pll0_config = {
    > .l = 0x47,
    > .alpha = 0xE000,
    > @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = {
    > { .compatible = "qcom,sc8180x-dispcc" },
    > { .compatible = "qcom,sm8150-dispcc" },
    > { .compatible = "qcom,sm8250-dispcc" },
    > + { .compatible = "qcom,sm8350-dispcc" },
    > { }
    > };
    > MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
    > @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
    > return PTR_ERR(regmap);
    > }
    >
    > - /* note: trion == lucid, except for the prepare() op */
    > + /* Apply differences for SM8150 and SM8350 */
    > BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
    > if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
    > of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
    > @@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
    > disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
    > disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
    > disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
    > + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
    > + static struct clk_rcg2 * const rcgs[] = {
    > + &disp_cc_mdss_byte0_clk_src,
    > + &disp_cc_mdss_byte1_clk_src,
    > + &disp_cc_mdss_dp_aux1_clk_src,
    > + &disp_cc_mdss_dp_aux_clk_src,
    > + &disp_cc_mdss_dp_link1_clk_src,
    > + &disp_cc_mdss_dp_link_clk_src,
    > + &disp_cc_mdss_dp_pixel1_clk_src,
    > + &disp_cc_mdss_dp_pixel2_clk_src,
    > + &disp_cc_mdss_dp_pixel_clk_src,
    > + &disp_cc_mdss_esc0_clk_src,
    > + &disp_cc_mdss_mdp_clk_src,
    > + &disp_cc_mdss_pclk0_clk_src,
    > + &disp_cc_mdss_pclk1_clk_src,
    > + &disp_cc_mdss_rot_clk_src,
    > + &disp_cc_mdss_vsync_clk_src,
    > + };
    > + static struct clk_regmap_div * const divs[] = {
    > + &disp_cc_mdss_byte0_div_clk_src,
    > + &disp_cc_mdss_byte1_div_clk_src,
    > + &disp_cc_mdss_dp_link1_div_clk_src,
    > + &disp_cc_mdss_dp_link_div_clk_src,
    > + };
    > + unsigned int i;
    > + static bool offset_applied;
    > +
    > + /* only apply the offsets once (in case of deferred probe) */
    > + if (!offset_applied) {
    > + for (i = 0; i < ARRAY_SIZE(rcgs); i++)
    > + rcgs[i]->cmd_rcgr -= 4;
    > +
    > + for (i = 0; i < ARRAY_SIZE(divs); i++) {
    > + divs[i]->reg -= 4;
    > + divs[i]->width = 4;
    > + }
    > +
    > + disp_cc_mdss_ahb_clk.halt_reg -= 4;
    > + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
    > +
    > + offset_applied = true;
    > + }
    > +
    > + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
    > +
    > + disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C;
    > + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
    > + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
    > + disp_cc_pll0.vco_table = lucid_5lpe_vco;
    > + disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C;
    > + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
    > + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
    > + disp_cc_pll1.vco_table = lucid_5lpe_vco;
    > }
    >
    > clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
    > --
    > 2.34.1
    >

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