Messages in this thread Patch in this message | | | From | medadyoung@gmail ... | Subject | [PATCH v11 3/3] EDAC: nuvoton: Add NPCM memory controller driver | Date | Fri, 27 May 2022 14:11:48 +0800 |
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From: Medad CChien <ctcchien@nuvoton.com>
Add memory controller support for Nuvoton NPCM SoC.
Note: you can force an ecc event by writing a string to edac sysfs node and remember to define CONFIG_EDAC_DEBUG to enable this feature example: force a correctable event on checkcode bit 0 echo "CE checkcode 0" to below path /sys/devices/system/edac/mc/mc0/forced_ecc_error
Datasheet: Cadence DDR Controller Register Reference Manual For DDR4 Memories Chapter 2: Detailed Register Map
Signed-off-by: Medad CChien <ctcchien@nuvoton.com> --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS index 7f832e6ed4e5..8919fb83f485 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2372,9 +2372,9 @@ F: arch/arm/boot/dts/nuvoton-npcm* F: arch/arm/mach-npcm/ F: drivers/*/*npcm* F: drivers/*/*/*npcm* +F: drivers/edac/npcm_edac.c b/drivers/edac/npcm_edac.c F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h - ARM/NUVOTON WPCM450 ARCHITECTURE M: Jonathan Neuschäfer <j.neuschaefer@gmx.net> L: openbmc@lists.ozlabs.org (moderated for non-subscribers) -- 2.17.1
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