Messages in this thread | | | From | Linus Torvalds <> | Date | Thu, 26 May 2022 10:23:58 -0700 | Subject | Re: [PATCH 2/2] locking/lockref/x86: Enable ARCH_USE_CMPXCHG_LOCKREF for X86_32 && X86_CMPXCHG64 |
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On Thu, May 26, 2022 at 1:30 AM David Laight <David.Laight@aculab.com> wrote: > > Perhaps there could be a non-smp implementation of cmpxchg8b > that just disables interrupts?
As Uros points out, we do have exactly that, but it's not actually written to be usable for the "trylock" case. Plus it would be pointless for lockrefs, since the non-cmpxchg case that just falls back to a spinlock would be faster and simpler (particularly on UP, where locking goes away).
> While I have used a dual 486 I doubt Linux would run ever > have on it. The same is probably true for old dual Pentiums.
Yeah, I don't think we ever supported SMP on i486, afaik they all needed special system glue.
I think the "modern" x86 SMP support with a local APIC was a PPro and newer thing historically, but clearly there were then later what amounted to Penitum/MMX class cores (ie old Atom) that did support SMP.
Linus
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