Messages in this thread Patch in this message | | | From | Ravi Bangoria <> | Subject | [PATCH 04/13] perf/x86/amd: Support PERF_SAMPLE_WEIGHT using IBS OP_DATA3[IbsDcMissLat] | Date | Wed, 25 May 2022 15:09:29 +0530 |
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IBS Op data3 provides data cache miss latency which can be passed as sample->weight along with perf_mem_data_src. Note that sample->weight will be populated only when PERF_SAMPLE_DATA_SRC is also set, although both sample types are independent.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> --- arch/x86/events/amd/ibs.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 6626caeed6a1..5a6e278713f4 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -738,6 +738,12 @@ static void perf_ibs_get_mem_lvl(struct perf_event *event, u64 op_data2, return; } + /* Load latency (Data cache miss latency) */ + if (data_src->mem_op == PERF_MEM_OP_LOAD && + event->attr.sample_type & PERF_SAMPLE_WEIGHT) { + data->weight.full = (op_data3 & IBS_DC_MISS_LAT_MASK) >> IBS_DC_MISS_LAT_SHIFT; + } + /* L2 Hit */ if ((op_data3 & IBS_L2_MISS_MASK) == 0) { /* Erratum #1293 */ -- 2.31.1
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