Messages in this thread | | | From | Miles Chen <> | Subject | Re: [PATCH v2 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock drivers | Date | Fri, 20 May 2022 17:35:01 +0800 |
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>> >> Thanks for submitting this patch. >> >> I compare this with drivers/clk/mediatek/clk-mt7986-apmixed.c, >> and other clk files are using macros to make the mtk_pll_data array >> more readable. > >I'd actually argue that macros make it less readable. While reading >other drivers I had a lot of trouble figuring out which argument >is which field of the struct, and had to constantly go back to the >macro definitions and count arguments to find it. Having it this >way, each value is labeled clearly with the field it's in. I think >the tradeoff between line count and readability here is worth it.
It is easier for multiple developers to work together if we have a common style.
How do you think?
Thanks, Miles
> >> >> Would you mind following the same style for all c files, please? >> >> e.g., >> static const struct mtk_pll_data plls[] = { >> PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32, >> 0x0200, 4, 0, 0x0204, 0), >> PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, >> 32, >> 0x0210, 4, 0, 0x0214, 0), >> ... >> }; >> >>> + }, >>> + .reg = APLL1_CON0, >>> + .pwr_reg = APLL1_PWR_CON0, >>> +module_platform_driver(clk_mt6735_apmixedsys); >>> + >>> +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); >>> +MODULE_DESCRIPTION("Mediatek MT6735 apmixedsys clock driver"); >> >> Would you mind changing all Mediatek to MediaTek? >> i.e., >> >> s/Mediatek/MediaTek/ >> > >Sure. Will fix it.
thanks > >> >> thanks, >> Miles >> +MODULE_LICENSE("GPL"); >> > >Thanks, >Yassine > > > >
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