Messages in this thread | | | From | Andy Shevchenko <> | Date | Thu, 19 May 2022 12:07:23 +0200 | Subject | Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support |
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On Thu, May 19, 2022 at 6:07 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko > <andy.shevchenko@gmail.com> wrote: > > On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
...
> > > GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is > > > handled by the pinctrl and IRQC driver. > > > > Where is the explanation on why valid_mask can't be used instead? > > > The .valid_mask option is one time setting but what I need is > something dynamic i.e. out of 392 GPIO pins any 32 can be used as an > interrupt pin. Also with this patch we also save on memory here [0].
Which internal APIs are bound to valid_mask not to be updated?
-- With Best Regards, Andy Shevchenko
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