Messages in this thread | | | Subject | Re: [PATCH] fpga: altera-cvp: allow interrupt to continue next time | From | Tom Rix <> | Date | Wed, 18 May 2022 07:04:34 -0700 |
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On 5/18/22 12:38 AM, tien.sung.ang@intel.com wrote: > From: Dinh Nguyen <dinh.nguyen@intel.com> > > CFG_READY signal/bit may time-out due to firmware not responding > within the given time-out. This time varies due to numerous > factors like size of bitstream and others. > This time-out error does not impact the result of the CvP > previous transactions. The CvP driver shall then, respond with > EAGAIN instead Time out error. > > Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com> > Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com> > --- > drivers/fpga/altera-cvp.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c > index 4ffb9da537d8..d74ff63c61e8 100644 > --- a/drivers/fpga/altera-cvp.c > +++ b/drivers/fpga/altera-cvp.c > @@ -309,10 +309,22 @@ static int altera_cvp_teardown(struct fpga_manager *mgr, > /* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */ > ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, > conf->priv->poll_time_us); > - if (ret) > + if (ret) { > dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n"); > + goto error_path; > + } > > return ret; > + > +error_path: > + /* reset CVP_MODE and HIP_CLK_SEL bit */ > + altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val); > + val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL; > + val &= ~VSE_CVP_MODE_CTRL_CVP_MODE; > + altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val); > + > + return -EAGAIN;
This will set fpga_mgr->state to *_ERR.
Is this ok or do you think we need a couple new of *_BUSY enums ?
Tom
> + > } > > static int altera_cvp_write_init(struct fpga_manager *mgr,
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