Messages in this thread | | | Date | Wed, 18 May 2022 19:04:28 +0800 | From | Zenithal <> | Subject | Re: [PATCH -next v2 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT |
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On Wed, May 18, 2022 at 09:50:18AM +0000, Conor.Dooley@microchip.com wrote: > On 18/05/2022 10:25, Hongren (Zenithal) Zheng wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > This commit parses Zb/Zk related string from DT and > > output them in cpuinfo > > Similarly here, the typical "this patch" comment.
Will fix in the next version.
> > > > > One thing worth noting is that if DT provides zk, > > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > > > Note that zk is a valid extension name and the current > > DT binding spec allows this. > > > > This commit also changes the logical id of > > "also" makes it sound like this a separate change? > If so, split it into another patch.
No, adding Zba naturally changes the logical id. I think it would be strange the first patch appends Zba then the second patch moves Zba to the beginning of the list
> > > existing multi-letter extensions and adds a statement > > that instead of logical id compatibility, the order > > is needed. > > > > There currently lacks a mechanism to merge them when > > producing cpuinfo. Namely if you provide a riscv,isa > > "rv64imafdc_zk_zks", the cpuinfo output would be > > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > > _zksh_zkt" > > > > Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> > > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
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