Messages in this thread | | | Date | Wed, 18 May 2022 06:27:07 +0900 | From | Stafford Horne <> | Subject | Re: [PATCH v2 01/13] openrisc: Add gcc machine instruction flag configuration |
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On Tue, May 17, 2022 at 09:54:58AM +0900, Stafford Horne wrote: > OpenRISC GCC supports flags to enable the backend to output instructions > if they are supported by a target processor. This patch adds > configuration flags to enable configuring these flags to tune the kernel > for a particular CPU configuration. > > In the future we could also enable all of these flags by default and > provide instruction emulation in the kernel to make these choices easier > for users but this is what we provide for now. > > Signed-off-by: Stafford Horne <shorne@gmail.com> > --- > arch/openrisc/Kconfig | 53 ++++++++++++++++++++++++++++++++++++++++++ > arch/openrisc/Makefile | 17 ++++++++++++++ > 2 files changed, 70 insertions(+) > > diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig > index 0d68adf6e02b..ea7eac20911a 100644 > --- a/arch/openrisc/Kconfig > +++ b/arch/openrisc/Kconfig > @@ -114,6 +114,59 @@ config OPENRISC_HAVE_INST_DIV > default y > help > Select this if your implementation has a hardware divide instruction > + > +config OPENRISC_HAVE_INST_CMOV > + bool "Have instruction l.cmov for conditional move" > + default y > + help > + This config enables gcc to generate l.cmov instructions when compiling > + the kernel which in general will improve performance and reduce the > + binary size. > + > + Select this if your implementation has support for the Class II > + l.cmov conistional move instruction. > + > + Say N if you are unsure. > + > +config OPENRISC_HAVE_INST_ROR > + bool "Have instruction l.ror for rotate right" > + default y > + help > + This config enables gcc to generate l.ror instructions when compiling > + the kernel which in general will improve performance and reduce the > + binary size. > + > + Select this if your implementation has support for the Class II > + l.ror rotate right instruction. > + > + Say N if you are unsure. > + > +config OPENRISC_HAVE_INST_RORI > + bool "Have instruction l.rori for rotate right with immediate" > + default y > + help > + This config enables gcc to generate l.rori instructions when compiling > + the kernel which in general will improve performance and reduce the > + binary size. > + > + Select this if your implementation has support for the Class II > + l.rori rotate right with immediate instruction. > + > + Say N if you are unsure. > + > +config OPENRISC_HAVE_INST_SEXT > + bool "Have instructions l.ext* for sign extension" > + default y > + help > + This config enables gcc to generate l.ext* instructions when compiling > + the kernel which in general will improve performance and reduce the > + binary size. > + > + Select this if your implementation has support for the Class II > + l.exths, l.extbs, l.exthz and l.extbz size extend instructions. > + > + Say N if you are unsure.
Looking at this again and when generating the defconfig, the default for these should be no,
-Stafford
> + > endmenu > > config NR_CPUS > diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile > index 760b734fb822..b446510173cd 100644 > --- a/arch/openrisc/Makefile > +++ b/arch/openrisc/Makefile > @@ -21,6 +21,7 @@ OBJCOPYFLAGS := -O binary -R .note -R .comment -S > LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) > > KBUILD_CFLAGS += -pipe -ffixed-r10 -D__linux__ > +KBUILD_CFLAGS += -msfimm -mshftimm > > all: vmlinux.bin > > @@ -38,6 +39,22 @@ else > KBUILD_CFLAGS += $(call cc-option,-msoft-div) > endif > > +ifeq ($(CONFIG_OPENRISC_HAVE_INST_CMOV),y) > + KBUILD_CFLAGS += $(call cc-option,-mcmov) > +endif > + > +ifeq ($(CONFIG_OPENRISC_HAVE_INST_ROR),y) > + KBUILD_CFLAGS += $(call cc-option,-mror) > +endif > + > +ifeq ($(CONFIG_OPENRISC_HAVE_INST_RORI),y) > + KBUILD_CFLAGS += $(call cc-option,-mrori) > +endif > + > +ifeq ($(CONFIG_OPENRISC_HAVE_INST_SEXT),y) > + KBUILD_CFLAGS += $(call cc-option,-msext) > +endif > + > head-y := arch/openrisc/kernel/head.o > > libs-y += $(LIBGCC) > -- > 2.31.1 >
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