Messages in this thread Patch in this message | | | From | Lai Jiangshan <> | Subject | [PATCH V2 3/7] x86: Mark __native_read_cr3() & native_write_cr3() as __always_inline | Date | Mon, 16 May 2022 21:17:34 +0800 |
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From: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Mark __native_read_cr3() & native_write_cr3() as __always_inline to ensure they are not instrumentable and in the .entry.text section if the caller is not instrumentable and in the .entry.text section.
It prepares for __native_read_cr3() and native_write_cr3() to be used in the C entry code for handling KPTI.
Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com> --- arch/x86/include/asm/special_insns.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 45b18eb94fa1..dbaee50abb3c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -42,14 +42,14 @@ static __always_inline void native_write_cr2(unsigned long val) asm volatile("mov %0,%%cr2": : "r" (val) : "memory"); } -static inline unsigned long __native_read_cr3(void) +static __always_inline unsigned long __native_read_cr3(void) { unsigned long val; asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : __FORCE_ORDER); return val; } -static inline void native_write_cr3(unsigned long val) +static __always_inline void native_write_cr3(unsigned long val) { asm volatile("mov %0,%%cr3": : "r" (val) : "memory"); } -- 2.19.1.6.gb485710b
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