Messages in this thread | | | Subject | Re: [PATCH 08/10] coresight: Remove legacy Trace ID allocation mechanism | From | "liuqi (BA)" <> | Date | Tue, 17 May 2022 11:56:44 +0800 |
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Hi Mike,
On 2022/3/9 4:49, Mike Leach wrote: > This static 'cpu * 2 + seed' was outdated and broken for systems with high > core counts (>46). > > This has been replaced by a dynamic allocation system. > > Signed-off-by: Mike Leach <mike.leach@linaro.org> > --- > include/linux/coresight-pmu.h | 12 ------------ > 1 file changed, 12 deletions(-)
Seems coresight_get_trace_id() in tools/include/linux/coresight-pmu.h need to be deleted too.
Thanks, Qi
> > diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h > index 4ac5c081af93..bb4eb4de3c77 100644 > --- a/include/linux/coresight-pmu.h > +++ b/include/linux/coresight-pmu.h > @@ -8,7 +8,6 @@ > #define _LINUX_CORESIGHT_PMU_H > > #define CORESIGHT_ETM_PMU_NAME "cs_etm" > -#define CORESIGHT_ETM_PMU_SEED 0x10 > > /* > * Below are the definition of bit offsets for perf option, and works as > @@ -32,15 +31,4 @@ > #define ETM4_CFG_BIT_RETSTK 12 > #define ETM4_CFG_BIT_VMID_OPT 15 > > -static inline int coresight_get_trace_id(int cpu) > -{ > - /* > - * A trace ID of value 0 is invalid, so let's start at some > - * random value that fits in 7 bits and go from there. Since > - * the common convention is to have data trace IDs be I(N) + 1, > - * set instruction trace IDs as a function of the CPU number. > - */ > - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); > -} > - > #endif >
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