Messages in this thread | | | Date | Mon, 16 May 2022 20:16:13 +0000 | From | Sean Christopherson <> | Subject | Re: [PATCH v3 19/34] KVM: nVMX: hyper-v: Enable L2 TLB flush |
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On Wed, May 11, 2022, Maxim Levitsky wrote: > On Thu, 2022-04-14 at 15:19 +0200, Vitaly Kuznetsov wrote: > > +/* > > + * Note, Hyper-V isn't actually stealing bit 28 from Intel, just abusing it by > > + * pairing it with architecturally impossible exit reasons. Bit 28 is set only > > + * on SMI exits to a SMI transfer monitor (STM) and if and only if a MTF VM-Exit > > + * is pending. I.e. it will never be set by hardware for non-SMI exits (there > > + * are only three), nor will it ever be set unless the VMM is an STM. > > I am sure that this will backfire this way or another. Their fault though...
Heh, that was my initial reaction too, but after working through the architecture I gotta hand it to the Hyper-V folks, it's very clever :-) And if we ever need a synthetic exit reason for PV KVM... :-)
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