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SubjectRe: [PATCH V3] arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs
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On 5/12/2022 4:31 PM, Shreyas K K wrote:
> Add KRYO4XX gold/big cores to the list of CPUs that need the
> repeat TLBI workaround. Apply this to the affected
> KRYO4XX cores (rcpe to rfpe).
>
> The variant and revision bits are implementation defined and are
> different from the their Cortex CPU counterparts on which they are
> based on, i.e., (r0p0 to r3p0) is equivalent to (rcpe to rfpe).
>
> Signed-off-by: Shreyas K K <quic_shrekk@quicinc.com>
> ---
>
> Changes in v2:
> * r2p0 and r3p0 are also affected by this erratum.
> * Add the corresponding cores (repe and rfpe) making the range rcpe to rfpe.
>
> Changes in v3:
> * Fix the CPU model macro.
>
> Documentation/arm64/silicon-errata.rst | 3 +++
> arch/arm64/kernel/cpu_errata.c | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index 466cb9e89047..d27db84d585e 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -189,6 +189,9 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 |
> +----------------+-----------------+-----------------+-----------------------------+
> +| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +
> +----------------+-----------------+-----------------+-----------------------------+
> | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
> +----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 4c9b5b4b7a0b..a0f3d0aaa3c5 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
> #ifdef CONFIG_ARM64_ERRATUM_1286807
> {
> ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
> + /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
> + ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
> },
> #endif
> {},

Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>

Thanks,
Sai

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