Messages in this thread Patch in this message | | | From | Wanpeng Li <> | Date | Thu, 12 May 2022 16:23:40 +0800 | Subject | Re: [PATCH v2 1/2] KVM: LAPIC: Disarm LAPIC timer includes pending timer around TSC deadline switch |
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On Wed, 11 May 2022 at 21:54, Paolo Bonzini <pbonzini@redhat.com> wrote: > > On 5/11/22 04:38, Wanpeng Li wrote: > > > > Fixes: 4427593258 (KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch) > > Signed-off-by: Wanpeng Li<wanpengli@tencent.com> > > --- > > Please write a testcase for this.
Something like this, however, it is not easy to catch the pending timer in this scenario.
diff --git a/x86/apic.c b/x86/apic.c index 23508ad..108c1c8 100644 --- a/x86/apic.c +++ b/x86/apic.c @@ -22,7 +22,7 @@ static void test_lapic_existence(void) #define TSC_DEADLINE_TIMER_VECTOR 0xef #define BROADCAST_VECTOR 0xcf
-static int tdt_count; +static int volatile tdt_count;
static void tsc_deadline_timer_isr(isr_regs_t *regs) { @@ -672,6 +672,18 @@ static void test_apic_change_mode(void) /* now tmcct == 0 and tmict != 0 */ apic_change_mode(APIC_LVT_TIMER_PERIODIC); report(!apic_read(APIC_TMCCT), "TMCCT should stay at zero"); + + handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr); + irq_enable(); + + apic_write(APIC_LVTT, APIC_LVT_TIMER_ONESHOT | + APIC_LVT_TIMER_VECTOR); + /* Divider == 1 */ + apic_write(APIC_TDCR, 0x0000000b); + + apic_write(APIC_TMICT, 0x999999); + enable_tsc_deadline_timer(); + while(tdt_count == 1); }
#define KVM_HC_SEND_IPI 10
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