lkml.org 
[lkml]   [2022]   [Apr]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.17 0123/1126] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
    Date
    From: Nishanth Menon <nm@ti.com>

    commit 8cae268b70f387ff9e697ccd62fb2384079124e7 upstream.

    Though GIC ARE option is disabled for no GIC-v2 compatibility,
    Cortex-A53 is free to implement the CPU interface as long as it
    communicates with the GIC using the stream protocol. This requires
    that the SoC integration mark out the PERIPHBASE[1] as reserved area
    within the SoC. See longer discussion in [2] for further information.

    Update the GIC register map to indicate offsets from PERIPHBASE based
    on [3]. Without doing this, systems like kvm will not function with
    gic-v2 emulation.

    [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
    [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
    [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map

    Cc: stable@vger.kernel.org # 5.10+
    Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC")
    Reported-by: Marc Zyngier <maz@kernel.org>
    Signed-off-by: Nishanth Menon <nm@ti.com>
    Acked-by: Marc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20220215201008.15235-2-nm@ti.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++-
    arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
    2 files changed, 5 insertions(+), 1 deletion(-)

    --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
    @@ -35,7 +35,10 @@
    #interrupt-cells = <3>;
    interrupt-controller;
    reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
    - <0x00 0x01880000 0x00 0x90000>; /* GICR */
    + <0x00 0x01880000 0x00 0x90000>, /* GICR */
    + <0x00 0x6f000000 0x00 0x2000>, /* GICC */
    + <0x00 0x6f010000 0x00 0x1000>, /* GICH */
    + <0x00 0x6f020000 0x00 0x2000>; /* GICV */
    /*
    * vcpumntirq:
    * virtual CPU interface maintenance interrupt
    --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
    @@ -86,6 +86,7 @@
    <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
    <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
    <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
    + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
    <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
    <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
    <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;

    \
     
     \ /
      Last update: 2022-04-05 09:52    [W:4.103 / U:0.016 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site