Messages in this thread | | | Date | Tue, 5 Apr 2022 13:50:21 +0530 | Subject | Re: [Patch v3 1/4] dt-bindings: Document Tegra CCPLEX Cluster | From | Sumit Gupta <> |
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On 04/04/22 21:51, Rob Herring wrote: > External email: Use caution opening links or attachments > > > On Mon, Apr 04, 2022 at 05:47:10PM +0530, Sumit Gupta wrote: >> The Tegra CPU COMPLEX CLUSTER area contains memory-mapped >> registers that initiate CPU frequency/voltage transitions. >> >> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> >> --- > > Changes from v2? None perhaps because you ignored my comments there. Sorry, i missed that mail. Will do the fix in v4.
> >> .../tegra/nvidia,tegra-ccplex-cluster.yaml | 52 +++++++++++++++++++ >> 1 file changed, 52 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml >> >> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml >> new file mode 100644 >> index 000000000000..d89457e0bd7d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml >> @@ -0,0 +1,52 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Farm%2Ftegra%2Fnvidia%2Ctegra-ccplex-cluster.yaml%23&data=04%7C01%7Csumitg%40nvidia.com%7Cb16581be5d9b4c2e302a08da16571fa0%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C637846861298835916%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=NnMO3XdVzZjEDcYd5k8uPY1o%2BuJwNiWuZoAoJTaoako%3D&reserved=0" >> +$schema: "https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Csumitg%40nvidia.com%7Cb16581be5d9b4c2e302a08da16571fa0%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C637846861298835916%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=xEIMU8P4LOYDwTFyuaeClH0%2F7Na%2F7w29Fm6VBxxNRQQ%3D&reserved=0" >> + >> +title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings >> + >> +maintainers: >> + - Sumit Gupta <sumitg@nvidia.com> >> + - Mikko Perttunen <mperttunen@nvidia.com> >> + - Jon Hunter <jonathanh@nvidia.com> >> + - Thierry Reding <thierry.reding@gmail.com> >> + >> +description: |+ >> + The Tegra CPU COMPLEX CLUSTER area contains memory-mapped >> + registers that initiate CPU frequency/voltage transitions. >> + >> +properties: >> + $nodename: >> + pattern: "ccplex@([0-9a-f]+)$" >> + >> + compatible: >> + enum: >> + - nvidia,tegra186-ccplex-cluster >> + - nvidia,tegra234-ccplex-cluster >> + >> + reg: >> + maxItems: 1 >> + >> + nvidia,bpmp: >> + $ref: '/schemas/types.yaml#/definitions/phandle' >> + description: | >> + Specifies the BPMP node that needs to be queried to get >> + operating point data for all CPUs. >> + >> +additionalProperties: true > > Additionally, true is only allowed for incomplete, common bindings which > this is not. > Ok, will remove "additionalProperties: true" in v4.
>> + >> +required: >> + - compatible >> + - reg >> + - nvidia,bpmp >> + - status >> + >> +examples: >> + - | >> + ccplex@e000000 { >> + compatible = "nvidia,tegra234-ccplex-cluster"; >> + reg = <0x0 0x0e000000 0x0 0x5ffff>; >> + nvidia,bpmp = <&bpmp>; >> + status = "okay"; >> + }; >> -- >> 2.17.1 >> >>
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