Messages in this thread | | | Date | Mon, 4 Apr 2022 10:01:03 +0200 | Subject | Re: [PATCH 0/3] Ensure Low period of SCL is correct | From | Neil Armstrong <> |
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Hi,
On 29/03/2022 00:31, Lucas Tanure wrote: > On Mon, 28 Mar 2022, 21:37 Kevin Hilman, <khilman@baylibre.com> wrote: >> >> Hi Lucas, >> >> Lucas Tanure <tanure@linux.com> writes: >> >>> The default duty cycle of 33% is less than the required >>> by the I2C specs for the LOW period of the SCL clock. >>> >>> So, for 100Khz or less, use 50%H/50%L duty cycle, and >>> for the clock above 100Khz, use 40%H/60%L duty cycle. >>> That ensures the low period of SCL is always more than >>> the minimum required by the specs at any given frequency. >> >> Thanks for the fixes! >> >> This is going to affect all SoCs, so ould you please summarize how your >> changes were tested, and on which SoCs & boards? >> >> Thanks, >> >> Kevin > > Hi, > > I only tested against the vim3 board, measured the bus with a Saleae > logic pro 16. > The measurements were with 100k, 400k, and a few in-between frequencies.
Thanks, it's a great addition to have !
> > Is that enough?
A test on GXL/GXM (VIM1 or VIM2) & GXBB (Odroid-C2) devices is lacking before we can merge this.
If I find some time, I'll have a try, but everyone is welcome testing this serie and report if it still works fine for them.
Vyacheslav, do you think you can test on your JetHub devices ? it would validate GXL & AXG.
Neil
> > Thanks > Lucas
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