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    Subject[PATCH 5.15 12/33] spi: cadence-quadspi: fix write completion support
    Date
    From: Dinh Nguyen <dinguyen@kernel.org>

    commit 98d948eb833104a094517401ed8be26ba3ce9935 upstream.

    Some versions of the Cadence QSPI controller does not have the write
    completion register implemented(CQSPI_REG_WR_COMPLETION_CTRL). On the
    Intel SoCFPGA platform the CQSPI_REG_WR_COMPLETION_CTRL register is
    not configured.

    Add a quirk to not write to the CQSPI_REG_WR_COMPLETION_CTRL register.

    Fixes: 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling)
    Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
    Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
    Link: https://lore.kernel.org/r/20211108200854.3616121-1-dinguyen@kernel.org
    Signed-off-by: Mark Brown <broonie@kernel.org>
    [IA: backported for linux=5.15.y]
    Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/spi/spi-cadence-quadspi.c | 24 +++++++++++++++++++++---
    1 file changed, 21 insertions(+), 3 deletions(-)

    --- a/drivers/spi/spi-cadence-quadspi.c
    +++ b/drivers/spi/spi-cadence-quadspi.c
    @@ -36,6 +36,7 @@
    /* Quirks */
    #define CQSPI_NEEDS_WR_DELAY BIT(0)
    #define CQSPI_DISABLE_DAC_MODE BIT(1)
    +#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)

    /* Capabilities */
    #define CQSPI_SUPPORTS_OCTAL BIT(0)
    @@ -83,6 +84,7 @@ struct cqspi_st {
    u32 wr_delay;
    bool use_direct_mode;
    struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
    + bool wr_completion;
    };

    struct cqspi_driver_platdata {
    @@ -797,9 +799,11 @@ static int cqspi_write_setup(struct cqsp
    * polling on the controller's side. spinand and spi-nor will take
    * care of polling the status register.
    */
    - reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
    - reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
    - writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
    + if (cqspi->wr_completion) {
    + reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
    + reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
    + writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
    + }

    reg = readl(reg_base + CQSPI_REG_SIZE);
    reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
    @@ -1532,6 +1536,10 @@ static int cqspi_probe(struct platform_d

    cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
    master->max_speed_hz = cqspi->master_ref_clk_hz;
    +
    + /* write completion is supported by default */
    + cqspi->wr_completion = true;
    +
    ddata = of_device_get_match_data(dev);
    if (ddata) {
    if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
    @@ -1541,6 +1549,8 @@ static int cqspi_probe(struct platform_d
    master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
    if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
    cqspi->use_direct_mode = true;
    + if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
    + cqspi->wr_completion = false;
    }

    ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
    @@ -1649,6 +1659,10 @@ static const struct cqspi_driver_platdat
    .quirks = CQSPI_DISABLE_DAC_MODE,
    };

    +static const struct cqspi_driver_platdata socfpga_qspi = {
    + .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION,
    +};
    +
    static const struct of_device_id cqspi_dt_ids[] = {
    {
    .compatible = "cdns,qspi-nor",
    @@ -1666,6 +1680,10 @@ static const struct of_device_id cqspi_d
    .compatible = "intel,lgm-qspi",
    .data = &intel_lgm_qspi,
    },
    + {
    + .compatible = "intel,socfpga-qspi",
    + .data = (void *)&socfpga_qspi,
    + },
    { /* end of table */ }
    };


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