Messages in this thread | | | From | Brian Norris <> | Date | Wed, 27 Apr 2022 14:47:55 -0700 | Subject | Re: [PATCH v3 2/3] soc: rockchip: power-domain: Replace dsb() with smb() |
| |
On Tue, Apr 26, 2022 at 5:25 PM Robin Murphy <robin.murphy@arm.com> wrote: > On 2022-04-27 00:55, Peter Geis wrote: > > On Mon, Apr 25, 2022 at 9:46 PM Brian Norris <briannorris@chromium.org> wrote: > >> > >> It's unclear if these are really needed at all, but seemingly their > >> purpose is only as a write barrier. Use the general macro instead of the > >> ARM-specific one. ... > >> - dsb(sy); > >> + wmb(); > > > > Just curious, shouldn't this be mb() instead of wmb()? > > From the arm64 barrier.h: > > > > #define mb() dsb(sy) > > #define wmb() dsb(st) > > As I mentioned on v2, that would be the literal translation, however > there's no concurrency since this is happening under a mutex, so there's > no other agent against whose accesses loads would need to be > synchronised, therefore the only logical reason those DSBs were ever > there at all must be to ensure that the prior store(s) have been issued > to their destination before proceeding. The history implies that this > dates all the way back to RK3288, where Armv7's argument-less DSB lacked > that distinction anyway.
Thanks Robin. I already tried to capture part of this in the commit message:
"It's unclear if these are really needed at all, but seemingly their purpose is only as a write barrier."
i.e., it's intentional that I'm making a change, not a literal translation.
I ran through a few tests on Rockchip RK3399, FWIW, although I suppose some nasty memory ordering bugs are not exactly the kind of thing that would fall out in smoke tests.
Brian
| |