Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock | Date | Mon, 25 Apr 2022 19:05:58 +0200 |
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On Mon, Apr 25 2022 at 16:15, Adrian Hunter wrote: > On 25/04/22 12:32, Thomas Gleixner wrote: >> It's hillarious, that we still cling to this pvclock abomination, while >> we happily expose TSC deadline timer to the guest. TSC virt scaling was >> implemented in hardware for a reason. > > So you are talking about changing VMX TCS Offset on every VM-Entry to try to hide > the time jumps when the VM is scheduled out? Or neglect that and just let the time > jumps happen? > > If changing VMX TCS Offset, how can TSC be kept consistent between each VCPU i.e. > wouldn't that mean each VCPU has to have the same VMX TSC Offset?
Obviously so. That's the only thing which makes sense, no?
Thanks,
tglx
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