Messages in this thread Patch in this message | | | From | Lu Baolu <> | Subject | [PATCH v2 2/4] iommu/vt-d: Set PGSNP bit in pasid table entry for SVA binding | Date | Thu, 21 Apr 2022 19:35:56 +0800 |
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This field make the requests snoop processor caches irrespective of other attributes in the request or other fields in paging structure entries used to translate the request.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> --- drivers/iommu/intel/svm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 23a38763c1d1..c720d1be992d 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -391,9 +391,12 @@ static struct iommu_sva *intel_svm_bind_mm(struct intel_iommu *iommu, } /* Setup the pasid table: */ - sflags = (flags & SVM_FLAG_SUPERVISOR_MODE) ? - PASID_FLAG_SUPERVISOR_MODE : 0; - sflags |= cpu_feature_enabled(X86_FEATURE_LA57) ? PASID_FLAG_FL5LP : 0; + sflags = PASID_FLAG_PAGE_SNOOP; + if (flags & SVM_FLAG_SUPERVISOR_MODE) + sflags |= PASID_FLAG_SUPERVISOR_MODE; + if (cpu_feature_enabled(X86_FEATURE_LA57)) + sflags |= PASID_FLAG_FL5LP; + spin_lock_irqsave(&iommu->lock, iflags); ret = intel_pasid_setup_first_level(iommu, dev, mm->pgd, mm->pasid, FLPT_DEFAULT_DID, sflags); -- 2.25.1
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