Messages in this thread Patch in this message | | | From | Sherry Sun <> | Subject | [PATCH V2 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR | Date | Thu, 21 Apr 2022 09:53:13 +0800 |
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Since zynqmp_get_error_info() is called during CE/UE interrupt, at the end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the interrupt handler will be called only once, so need to re-enable the interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> --- Changes in V2: 1. Add the Reviewed-by and Acked-by tag. 2. Add the newline as suggested by Michal. --- drivers/edac/synopsys_edac.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 88a481043d4c..ae1cf02a92f5 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -527,6 +527,8 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) memset(p, 0, sizeof(*p)); } +static void enable_intr(struct synps_edac_priv *priv); + /** * intr_handler - Interrupt Handler for ECC interrupts. * @irq: IRQ number. @@ -568,6 +570,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id) /* v3.0 of the controller does not have this register */ if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); + else + enable_intr(priv); + return IRQ_HANDLED; } -- 2.17.1
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