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SubjectRe: [PATCH v7 5/8] KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode
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On 4/1/2022 7:07 AM, Sean Christopherson wrote:
> On Fri, Mar 04, 2022, Zeng Guang wrote:
>> Upcoming Intel CPUs will support virtual x2APIC MSR writes to the vICR,
>> i.e. will trap and generate an APIC-write VM-Exit instead of intercepting
>> the WRMSR. Add support for handling "nodecode" x2APIC writes, which
>> were previously impossible.
>>
>> Note, x2APIC MSR writes are 64 bits wide.
>>
>> Signed-off-by: Zeng Guang <guang.zeng@intel.com>
>> ---
>> arch/x86/kvm/lapic.c | 22 +++++++++++++++++++---
>> 1 file changed, 19 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>> index 629c116b0d3e..22929b5b3f9b 100644
>> --- a/arch/x86/kvm/lapic.c
>> +++ b/arch/x86/kvm/lapic.c
>> @@ -67,6 +67,7 @@ static bool lapic_timer_advance_dynamic __read_mostly;
>> #define LAPIC_TIMER_ADVANCE_NS_MAX 5000
>> /* step-by-step approximation to mitigate fluctuation */
>> #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
>> +static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
>>
>> static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
>> {
>> @@ -2227,10 +2228,25 @@ EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
>> /* emulate APIC access in a trap manner */
>> void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
>> {
>> - u32 val = kvm_lapic_get_reg(vcpu->arch.apic, offset);
>> + struct kvm_lapic *apic = vcpu->arch.apic;
>> + u64 val;
>> +
>> + if (apic_x2apic_mode(apic)) {
>> + /*
>> + * When guest APIC is in x2APIC mode and IPI virtualization
>> + * is enabled, accessing APIC_ICR may cause trap-like VM-exit
>> + * on Intel hardware. Other offsets are not possible.
>> + */
>> + if (WARN_ON_ONCE(offset != APIC_ICR))
>> + return;
>>
>> - /* TODO: optimize to just emulate side effect w/o one more write */
>> - kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
>> + kvm_lapic_msr_read(apic, offset, &val);
>> + kvm_apic_send_ipi(apic, (u32)val, (u32)(val >> 32));
> This needs to clear the APIC_ICR_BUSY bit. It'd also be nice to trace this write.
> The easiest thing is to use kvm_x2apic_icr_write(). Kinda silly as it'll generate
> an extra write, but on the plus side the TODO comment doesn't have to move :-D
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index c4c3155d98db..58bf296ee313 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2230,6 +2230,7 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
> struct kvm_lapic *apic = vcpu->arch.apic;
> u64 val;
>
> + /* TODO: optimize to just emulate side effect w/o one more write */
> if (apic_x2apic_mode(apic)) {
> /*
> * When guest APIC is in x2APIC mode and IPI virtualization
> @@ -2240,10 +2241,9 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
> return;
>
> kvm_lapic_msr_read(apic, offset, &val);
> - kvm_apic_send_ipi(apic, (u32)val, (u32)(val >> 32));
> + kvm_x2apic_icr_write(apic, val);

As SDM section 10.12.9 "ICR Operation in X2APIC mode" says "Delivery status
bit is removed since it is not needed in x2APIC mode" , so that's not
necessary
to clear the APIC_ICR_BUSY bit here. Alternatively we can add trace to
this write
by hardware.


> } else {
> val = kvm_lapic_get_reg(apic, offset);
> - /* TODO: optimize to just emulate side effect w/o one more write */
> kvm_lapic_reg_write(apic, offset, (u32)val);
> }
> }
>
>
>> + } else {
>> + val = kvm_lapic_get_reg(apic, offset);
>> + /* TODO: optimize to just emulate side effect w/o one more write */
>> + kvm_lapic_reg_write(apic, offset, (u32)val);
>> + }
>> }
>> EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
>>
>> --
>> 2.27.0
>>

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