Messages in this thread | | | Date | Tue, 19 Apr 2022 15:29:19 +0800 | Subject | Re: [PATCH V2 1/2] tty: serial: meson: Add a 12MHz internal clock rate to calculate baud rate in order to meet the baud rate requirements of special BT modules | From | Yu Tu <> |
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Hi Andy, Thank you for your advice.
On 2022/4/18 20:09, Andy Shevchenko wrote: > [ EXTERNAL EMAIL ] > > On Mon, Apr 18, 2022 at 8:50 AM Yu Tu <yu.tu@amlogic.com> wrote: >> >> A /2 divider over XTAL was introduced since G12A, and is preferred >> to be used over the still present /3 divider since it provides much >> closer frequencies vs the request baudrate.Especially the BT module > > 'e. E' (mind the space) My statement is a whole. There should be no spaces. > >> uses 3Mhz baud rate. 8Mhz calculations can lead to baud rate bias, >> causing some problems. > > ... > >> +struct meson_uart_data { >> + bool has_xtal_div2; > > I would prefer to see this as an unsigned int and with a less > particular name, e.g. xtal_div would suffice. I don't have a problem with your suggestion.Let's see What Neil has to say. > >> +}; > > ... > >> + unsigned int xtal_div = 3; > >> + if (private_data && private_data->has_xtal_div2) { >> + xtal_div = 2; > > Better to define privata data always > > >> + val |= AML_UART_BAUD_XTAL_DIV2; >> + } >> + val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1; > >
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