| Date | Thu, 14 Apr 2022 14:02:10 +0100 | From | "Russell King (Oracle)" <> | Subject | Re: [PATCH net-next 06/12] net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver |
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On Thu, Apr 14, 2022 at 02:22:44PM +0200, Clément Léger wrote: > Add Renesas RZ/N1 advanced 5 port switch driver. This switch handles 5 > ports including 1 CPU management port. A MDIO bus is also exposed by > this switch and allows to communicate with PHYs connected to the ports. > Each switch port (except for the CPU management ports) are connected to > the MII converter. > > This driver include basic bridging support, more support will be added > later (vlan, etc).
This patch looks to me like it needs to be updated...
> +static void a5psw_phylink_validate(struct dsa_switch *ds, int port, > + unsigned long *supported, > + struct phylink_link_state *state) > +{ > + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0 }; > + > + phylink_set_port_modes(mask); > + > + phylink_set(mask, Autoneg); > + phylink_set(mask, Pause); > + phylink_set(mask, Asym_Pause); > + > + phylink_set(mask, 1000baseT_Full); > + if (!dsa_is_cpu_port(ds, port)) { > + phylink_set(mask, 10baseT_Half); > + phylink_set(mask, 10baseT_Full); > + phylink_set(mask, 100baseT_Half); > + phylink_set(mask, 100baseT_Full); > + }
If the port supports e.g. RGMII (as it does via the media converter) then it also supports 1000baseX modes as well - because a PHY attached to the RGMII port can convert to 1000baseX.
> + > + linkmode_and(supported, supported, mask); > + linkmode_and(state->advertising, state->advertising, mask); > +}
This basically means "I support every phy_interface_t mode that has ever been implemented" which surely is not what you want. I doubt from the above that you support 10GBASE-KR for example.
Please instead implement the .phylink_get_caps DSA switch interface, and fill in the config->supported_interfaces for all interface modes that the port supports (that including the media converter as well) and the config->mac_capabilities members.
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