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    Subject[PATCH v6 05/13] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
    Date
    From: Jacky Bai <ping.bai@nxp.com>

    On i.MX8DXL, the LSIO subsystem includes below devices:

    1x Inline Encryption Engine (IEE)
    1x FlexSPI
    4x Pulse Width Modulator (PWM)
    5x General Purpose Timer (GPT)
    8x GPIO
    14x Message Unit (MU)
    256KB On-Chip Memory (OCRAM)

    compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
    property need to be updated.

    Signed-off-by: Jacky Bai <ping.bai@nxp.com>
    Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
    ---
    .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 78 +++++++++++++++++++
    1 file changed, 78 insertions(+)
    create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi

    diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
    new file mode 100644
    index 000000000000..6aec2ec3a848
    --- /dev/null
    +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
    @@ -0,0 +1,78 @@
    +// SPDX-License-Identifier: GPL-2.0+
    +/*
    + * Copyright 2019-2021 NXP
    + */
    +&lsio_gpio0 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_gpio1 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_gpio2 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_gpio3 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_gpio4 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_gpio5 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_gpio6 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_gpio7 {
    + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
    + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_mu0 {
    + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_mu1 {
    + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_mu2 {
    + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_mu3 {
    + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_mu4 {
    + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_mu5 {
    + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
    +};
    +
    +&lsio_mu13 {
    + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
    + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
    +};
    --
    2.34.1
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